The present invention relates to a data-readable/writable semiconductor memory device using a MOS transistor as a memory element.
As shown in FIG. 1, a nonvolatile transistor used as a memory cell of an EEPROM for electrically erasing data is formed of two polycrystalline silicon layers insulated from each other by an insulating film.
A first polycrystalline silicon layer forms a floating gate 701 and a second polycrystalline silicon layer forms a control gate 702. A reference numeral 703 denotes a source, 704 a drain, 705 a silicon substrate, 706 a contact hole and 707 a data line formed of Al (aluminum). The data line 707 is connected to the drain 704 through a contact hole 706.
Operations of writing, reading and erasing data in the memory cell having the aforementioned structure will be described below.
A writing operation is performed by setting a drain potential V.sub.D to 5.5V, a control gate potential V.sub.CG to 10V and a source potential V.sub.S to 0V, and injecting hot electrons into the floating gate.
An erasing operation is performed by setting a control gate potential V.sub.CG to -7V and setting a drain potential V.sub.D in a floating state, and applying a voltage of, for example, 6.5V to the source. At this time, electrons are extracted from the floating gate to the source by tunnel effect.
A reading operation is performed by setting a control gate potential V.sub.CG to -7V, a drain potential V.sub.D to 0.8V, and a source potential V.sub.S to 0V. At this time, if the memory data in the memory cell is "0" (write state), substantially no current flows between the source and the drain. If the memory data is "1" (erase state), a cell current of about 60 .mu. A flows between the source and the drain.
Memory cell arrays including memory cells as described above are arranged as shown in FIG. 2, divided into blocks B.sub.0 to B.sub.j, each including memory cell arrays IO.sub.0 to IO.sub.i, so that data can be partially written and erased. The term "block" means a unit for performing writing/erasing operations.
In FIG. 2, the memory cell arrays IO.sub.0 to IO.sub.i, divided into blocks, are respectively connected to data bus lines DL.sub.0 to DL.sub.i through column gates 11. The data bus lines DL.sub.0 to DL.sub.i are respectively connected to buffer circuits 13.sub.0 to 13.sub.i through, for example, sense amplifiers 12.sub.0 to 12.sub.i.
The data bus lines DL.sub.0 to DL.sub.i are respectively connected to load circuits 14.sub.0 to 14.sub.i, each having a comparatively large-size transistor. The load circuits are collected in a group away from the memory cell arrays. Therefore, due to parasitic resistance of the data bus lines DL.sub.0 to DL.sub.i, a difference in potential drop is made between the block B.sub.0 near the group of load circuits and a block B.sub.j far from them. Accordingly, the writing characteristic in the former block is different from that of the latter.
FIG. 3 is a circuit diagram showing a structure of a load circuit 14.sub.i of the load circuits 14.sub.0 to 14.sub.i.
The load circuit comprises a load transistor circuit, in which an N-channel MOS transistor Tr is connected between a power source VPOWER and a data line DL.sub.i.
A gate input PRGH.sub.i input to the transistor Tr is high in potential, when write data to be supplied to a memory cell is "0". At this time, the drain potential is transmitted to the memory cell. On the other hand, when write data is "1", the gate input PRGH.sub.i is equal to a ground potential. At this time, the drain of the memory cell is in a floating state, and therefore no writing operation is performed.
As described above, the prior art has the following drawbacks.
In the conventional semiconductor memory device, since the load circuits (comparatively great load circuits), functioning in a writing operation, are collected in a group away from the memory cell arrays and connected to the corresponding blocks of the memory cell arrays only by the data bus lines, a difference in writing characteristic is made between a block near the group of load circuits and a block far from them, due to parasitic resistance of the data bus lines.